| 摘要 |
A method of etching tantalum oxide layer in the fabrication of dynamic random access memory (DRAM). The method comprises the steps of forming the lower electrode structure of a capacitor on a semiconductor substrate. Then, a tantalum oxide layer, a barrier layer and a conductive layer are sequentially formed over the lower electrode structure and the substrate. Next, the conductive layer is patterned using a first reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl3/Cl2/N2). Thereafter, the barrier layer is patterned using a second reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl3/Cl2/N2). Finally, the tantalum oxide layer is patterned using a third reactive gas that includes a gaseous mixture of boron trichloride, chlorine and nitrogen (BCl3/Cl2/N2).
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