| 摘要 |
A process is described wherein logic and memory share the same chip. Contacts to the gates in the memory areas are made using a silicide process, while contacts to the logic circuits are made using the SALICIDE process, thus ensuring high performance. The two processes have been integrated within a single chip by first covering the gate pedestals in both areas with a layer of cap oxide. The wafer is then covered with a layer of BARC (Bottom Anti-Reflection Coating) which is etched back so as to expose only the cap oxide that covers the top surfaces of the gate pedestals. This allows the cap oxide to be removed from only these top surfaces. In an alternative embodiment, photoresist may be used in place of BARC. The remaining cap oxide is then selectively removed in only the logic area and the standard SALICIDE process is applied, resulting in SALICIDE contacts to source, gate, and drain on the logic side and silicide contacts to the gates on the memory side.
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