发明名称 SLEW RATE OUTPUT CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a slew rate output circuit, which maintains a slew rate function and reduces a delay time of an output waveform by switch controlling a value of a constant current which charges and discharges an input capacitance of an output transistor. SOLUTION: A delaying circuit D1 and a NAND gate G1 generate a signal Va , which becomes a low level only for a short fixed time T1 from the time when an input pulse signal Vin transits from a low level to a high level. Also, a delaying circuit D2 and a NOR gate G2 generate a signal Vb , which becomes a high level only for a short fixed time T2 from a point of time when the input pulse signal Vin , transits from the high level to the low level. The signal Va is connected to a P-channel transistor Q1 and a signal VD is connected to an N-channel transistor Q2 respectively. As a result, an output transistor Q0 is driven by the input pulse signal by way of a resistor R0 and by a drain of the P-channel transistor Q1 by way of a resistor R1 during a period T1 , by the input pulse signal Vin by way of a resistor R0 and by the drain of the N-channel transistor by way of a resistor R2 during a period of T2 , and only the input pulse signal Vin by way of the resistor R0 during other periods respectively.
申请公布号 JPH11346147(A) 申请公布日期 1999.12.14
申请号 JP19980152624 申请日期 1998.06.02
申请人 NEC CORP 发明人 MITSUDA TAKESHI
分类号 H03K17/04;H03K17/16;H03K17/687;H03K19/00;H03K19/003 主分类号 H03K17/04
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