| 摘要 |
<p>PROBLEM TO BE SOLVED: To shorten the fall time of a power semiconductor device, lower the turning-on voltage of the device, and improve the load short-circuiting resistance of the device by specifying the sizes of an emitter layer of a first conductivity and a contact layer of a second conductivity in the channel widthwise direction. SOLUTION: When the sizes W1 and W2 of an n-type emitter layer 8 and a p-type contact layer 9 in the channel widthwise direction meets a relation, W1/(W1+W2)<=0.4, sizes in an IGBT, the fall time of a power semiconductor device when the device is turned off can be shortened while the increase of the turning-on voltage of the device is suppressed. When the size of the emitter layer 8 in the channel widthwise direction is adjusted to <=3μm, the latch-up resistance and load short-circuiting resistance of the device can be improved by scarcely raising the turning-on voltage. In addition, since the emitter layer 8 is not brought into contact with an emitter electrode even partially, carriers can be stored in an element and the turning-on voltage of the device can be lowered.</p> |
