| 摘要 |
A computer system comprising a processor, a memory subsystem having a fast memory and a slow memory, and other at least one peripheral-performing variable length processor write cycles is described. The present invention includes a method and apparatus for generating signals to indicate write cycles to either a fast memory or a slow memory. The present invention also includes a method of generating signals to indicate the initiation of write cycle to a slow memory and avoiding the insertion of unnecessary wait states in write cycles to memory. The present invention further includes a method of minimizing wait states in a write cycle to memory. The computer system further includes a memory controller having a control flag signal to indicate a write to slow memory when asserted, and to indicate a write to a fast memory when deasserted. The control flag signal when asserted memory system includes a programmable address decoder having a writable memory which provides bank address signals.
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