| 摘要 |
PROBLEM TO BE SOLVED: To exclude comparison exceptions between an expected value and a result value in logical verification by logical simulation and to permit logical verification with higher precision by generating expected values in the same execution order with a tested logic unit with a test signal sequence depending upon the execution order. SOLUTION: A control unit execution order monitor device 103 retrieves the order of storage in a test signal sequence file 106 in logical simulation and stores the test signal execution order of a control unit 104 in an execution order storage file 107. After the logical simulation ends, an information processor simulator 100 generates result values in a result value file 109 from a main storage unit 105. A control unit emulator 108 takes the test signal sequence out in the execution order of the execution order storage file 107 and generates an expected value by emulation. A result editing device 111 compares the expected value with the execution result of the result value file 109 to decide whether or not the logical simulation result is proper. |
