| 摘要 |
PROBLEM TO BE SOLVED: To provide a shift register circuit capable of a stable operation over all steps by suppressing the delay of a clock signal and the slippage of an output timing between blocks, and to improve a display quality of a device by applying the shift resistor circuit to an image display device. SOLUTION: Clock buffer circuits 11, 11 are arranged corresponding to plural latch circuit groups (BLK1, BLK2,...). The clock buffer circuits 11, 11 have a function to generate local clock signals LCK./LCK to be supplied to latch circuits 6, from inputted global clock signals GCK./GCK. Local clock signal lines 7, 8, installed corresponding to each latch circuit group, are connected mutually among each latch circuit group. Hereby, the clock signals are leveled mutually among each latch circuit group. In an image display device in which a driving circuit and a display region are formed integrally, a data signal line driving circuit, for example, is formed by the shift resister circuit 5. |
