| 摘要 |
PROBLEM TO BE SOLVED: To suppress occurrence of erroneous operation resulting from transmission lag of clock pulse while preventing occurrence of abnormal driving state of a load. SOLUTION: When a bidirectional shift register 21 is shifted to the right, a clock supply circuit 29 switches a first buffer circuit 30 to high impedance state and a second buffer circuit 31 to low impedance state in response to a low level switching command signal Sc provided at a switching terminal 33 and delivers a clock pulse Pc in the direction of an arrow B to a clock line 27. When the bidirectional shift register 21 is shifted to the left, the clock supply circuit 29 switches the first buffer circuit 30 to low impedance state and the second buffer circuit 31 to high impedance state in response to a high level switching command signal Sc provided at the switching terminal 33 and delivers a clock pulse Pc in the direction of an arrow A to the clock line 27. |
