| 发明名称 |
Hierarchical bus structure with preprocessing processors |
| 摘要 |
The computer system includes a hierarchal bus with bus couplers between each layer. Main memory (2) and the CPU (1) are connected to the top bus system (3) and input/output devices (102a-102f) are connected to the lower bus system (5a-5c). Processors (9a-9c) are included on the lower bus system to handled fixed preprocessing of data.
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| 申请公布号 |
DE19901792(A1) |
申请公布日期 |
1999.12.09 |
| 申请号 |
DE19991001792 |
申请日期 |
1999.01.08 |
| 申请人 |
MITSUBISHI DENKI K.K., TOKIO/TOKYO |
发明人 |
MITSUNORI, KORI |
| 分类号 |
G06F13/36;G06F13/40;G06F15/173;G06F15/177;(IPC1-7):G06F13/38;G06F13/12 |
主分类号 |
G06F13/36 |
| 代理机构 |
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代理人 |
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| 主权项 |
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