| 摘要 |
1281808 Transistor bi-stable circuits INTERNATIONAL BUSINESS MACHINES CORP 19 April 1971 [20 April 1970] 26433/71 Heading H3T [Also in Division G4] Each cell of an associative storage array comprises a pair of cross-coupled transistors T1, T2 and a pair of input/output transistors T3, T4 connected as shown. A further pair of load transistors T5, T6 of conductivity opposite type to transistors T1, T2 may be provided between points A, B and a control voltage source V 1 . In a normal read operation, the potential of word line W/L is raised so that the transistor T3 or T4 with its base connected to that of the conducting transistor T2 or T1 conducts to provide an output on the B 1 or B0 bit line, the transistors T3, T4 being held non-conductive while the cell is not being accessed. In a write operation, the potential of the B0 or B1 bit line is decreased while that of the word line is raised to cause T3 or T4 to conduct and reduce the potential at point A or B until the transistor T1 or T2 with its base connected to that point is biased off and the other transistor T2 or T1 on. To perform associative read-out, the potential of bit line B0 or B1 is lowered to approximately that of the word line. If the cell is in the "1" state with T2 on, and a search for a "0" bit is made by lowering the potential of bit line B1, T3 conducts to cause current flow in the associative sense line A/S which is detected as a mismatch by amplifier 28. If the cell is in the "O" state with T1 on, T3 does not conduct, and if all cells connected to common line A/S similarly indicate matching conditions, a match output is obtained from amplifier 28. Voltage V1 may be varied to make the resistance of the cell very low so that read and write operations can be made rapidly with low power dissipation.
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