Low power memory including selective precharge circuit

摘要

A low power RAM device including a bit line precharge circuit which selectively precharges only those bit lines which will be read in an effort to minimize precharge and overall RAM power consumption. The preferred RAM precharge circuit uses a precharge device in the sense amplifier as the primary bit line precharge device to selectively connect and precharge the selected bit line through a column MUX. The preferred RAM precharge also includes secondary bit line precharge devices for each bit line to enable trickle charging thereof to prevent hazardous RAM data corruption. Since RAM corruption occurs only after several clock cycles, the secondary precharge devices comprise small transistors having only 1/20 the size of normal precharge device to conserve precharge power requirements. The RAM device includes a carefully controlled timing sequence of precharge signal, column-select signals, and word-line signals, to selective precharge the selected bit line and to remove the hazardous power consuming DC current path to further reduce power consumption therein.