Signal generator using digital phase locked loops

摘要

The generator produces a drive signal for input to monitor with a phase difference with respect to a signal from an external synchronization, and comprises three blocks. The main block (PLL2) contains a circuit (CME) for measuring the front of the drive signal front position or of the retarded signal with respect to a reference signal input from block (PLL1), and a circuit for digital calculation of phase difference (CCN). The measurement circuit (CME) includes gross measurement circuit (CMG) controlled by fixed phase high frequency signal and fine measurement circuit (CMF) corresponding to an ultra-high frequency. A set of signals defining N phases is input from block (PLL0), that a voltage controlled oscillator (VCO). The high frequency F applied to each block is e.g. 192 MHz, and the ultra-high frequency for fine measurement corresponding to a fictitious clock rate is e.g. 3.2 GHz. The fine measurement is carried out by input of the set of N, e.g. 16, phases to the memory of the circuit (CMF).