Weak inversion NMOS regulator with boosted gate

摘要

A voltage regulator for DRAM chips having known short duration high current load events started by a trigger signal includes a regulating transistor operating in the weak inversion mode and a boost driver circuit. The trigger signal that starts the load event also triggers the boost driver circuit to produce a shaped boost signal at the correct time. The boost signal is applied to the gate of the regulating transistor to counteract the expected voltage drop at the output of the regulating transistor. The expected voltage drop is due to the known characteristics of the regulating transistor which include a change in threshold voltage of the regulating transistor during the high current flow of the load event. A switch device disconnects a preregulator during the load event and reconnects the preregulator thereafter. The boost signal is preferably applied to the regulating transistor through a capacitive divider.