| 摘要 |
A layout parasitics extraction system. The layout parasitics extraction system is a connectivity-based approach for extracting layout parasitics. The system creates a connectivity-based database (1104), where geometries of a layout are organized by nets of the circuit schematic. The system allows net-by-net extraction (1124) of layout parasitics using a connectivity-based database. A user can select a net or nets for extraction. The system creates a database containing nets and their extracted layout parasitics (1132). The system can generate a netlist format file from this database to provide for back annotation of layout parasitics into a circuit schematic for further circuit analysis.
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