| 摘要 |
A ferroelectric storage device enabling an increase of capacity without a major increase in the chip size by use of multi-level data. At the time of a write operation, one of four types of potential based on the 2 bits of data input to the I/O terminal is selectively supplied from a potential generator to a bit line through a data line. The potential is supplied to one of the electrodes of a ferroelectric capacitor where one of four types of residual polarization states is selectively produced at the ferroelectric. By this, 4-level data is stored in a single memory cell. At the time of a read operation, the potential of the bit line is compared with three reference potentials at an output data generator to discriminate the stored data.
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