| 摘要 |
A clock forwarding circuit of a semiconductor integrated circuit which increases an operation timing margin of a data receive port and reduces power consumption, and a clock forwarding method, are provided. In the clock forwarding circuit for performing the clock forwarding method, upon abnormal operation of the semiconductor integrated circuit, such as during power-up or initialization, the data receive port captures the amount of interconnection delay of a data line and generates a receive clock signal which is self-generated, from a delayed send clock transmitted from a data send port via the data line. On the other hand, when the circuit operates in a normal operation mode, the data receive port receives data transmitted from the data send port via the data line, in response to the self-generated receive clock. Accordingly, the amount of interconnection delay of the data line is previously captured and data is received in response to the self-generated receive clock. Thus, the operation timing margin of the data receive port is increased. Also, a separate clock line is not required, and the send clock is supplied to the data receive port via the data line only upon abnormal operation of the semiconductor integrated circuit, so that power consumption is reduced.
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