发明名称 Circuit arrangement for burn in system for testing chips using board
摘要 The circuit arrangement is used for burn-in systems for testing chips by means of a board. The chips are arranged in a matrix arrangement in the board. In the board the chips can be connected to input/output channels (4,5) and are activated group-wise by scan signals (1). For each scan signal (1), an input channel is provided via a diode (2,3) to activate the input/output channel (4,5). Preferably the chip is a memory. When data is written into the memory, both input channels associated with a scan signal are activated simultaneously. On reading data from the memory these input channels (4,5) are sequentially activated.
申请公布号 DE19823943(A1) 申请公布日期 1999.12.02
申请号 DE19981023943 申请日期 1998.05.28
申请人 SIEMENS AG 发明人 SILLUP, JOSEPH;WEBER, FRANK
分类号 G11C29/56;G01R31/3185;H01L21/66;(IPC1-7):G11C29/00 主分类号 G11C29/56
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