发明名称 |
Defect analysis apparatus for the inspection of an integrated circuit (IC) such as a dynamic random access memory (DRAM) |
摘要 |
Defect information is extracted from an input fail bit map. A converter applies a two-dimensional wavelet conversion process to the input fail bit map. An image output device outputs the wavelet conversion result as an image information. An Independent claim is also included for a defect analysis.
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申请公布号 |
DE19919157(A1) |
申请公布日期 |
1999.12.02 |
申请号 |
DE19991019157 |
申请日期 |
1999.04.27 |
申请人 |
ADVANTEST CORP., TOKIO/TOKYO |
发明人 |
FUJIWARA, TERUAKI;MARUO, KAZUYUKI;YAMAGUCHI, TAKAHIRO |
分类号 |
G01R31/3193;G06T1/00;G11C29/44;G11C29/56;(IPC1-7):G06F11/00;G01R31/317;G11C29/00 |
主分类号 |
G01R31/3193 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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