Parity error identification in a multiple processor system

摘要

An array of signal processing integrated circuits (SPICs) connected to communicate data via one or more buses in which each processor includes a parity generator to apply parity to data output to the buses, a parity checker 25 which checks the parity of data received over the buses and signals an error 65,71 if a parity error occurs, and a register 70 which stores a count indicating the clock cycle at which any parity error occurs. On detection of a parity error the checker 25 generates the interrupt signal 65 which is supplied to the interrupt output of the SPIC. This signal also interrupts a control processor 26 which reads the count in the register 70. The value read from the register can then be used by the control processor or a human operator to trace the SPIC from which the source of the parity error originated. The SPIC array itself may be used as part of a digital audio data processing system.