| 摘要 |
<p>A delay locked loop clock circuit (10) employs an analog control loop for generating picosecond-accurate clock delays. A linear analog comparison circuit operating on integrated DC levels replaces the usual digital phase comparator for substantially improved timing accuracy. In operation, clock pulses from a first delay path (14) are integrated (18) and applied to a loop control amplifier (26). Clock pulses from a second delay path (16) are integrated (20) and applied to a differencing input of the loop control amplifier (26). The loop control amplifier (26) regulates the delay in the second delay path (16) to balance the integrated clock pulse voltage against externally applied control voltages (24, 26). The delay between the first path and the second path is thereby precisely controlled by external voltage inputs. The first and second path clock output timing relationship is directly measured by analog voltage devices, eliminating error-prone high-speed phase comparators employed in prior art approaches.</p> |
