发明名称 Method and circuit for automatic phase and frequency adjustment of a regenerated clock in a digital image display apparatus
摘要 An digital image display apparatus (IDA) converting an analog image input signal (Sia) into digital form to display images has an A/D converting unit (ADCU) for converting the analog image input signal (Sia) into a digital image signal (Sid) in a given cycle based on a clock (Scd) and phase data (Sp), an image start/termination coordinate detector (3) for detecting horizontal image start coordinates (HcS) and horizontal image termination coordinates (HcE) in a horizontal period (Ph1 - Ph2) based on the digital image signal (Sid), a horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync), and a clock (Sc), an image start/termination storage (6) for storing the horizontal image start coordinates (HcS) and the horizontal image termination coordinates (HcE) related to the phase data in the A/D converting unit (ADCU), a display controller (4R) for outputting the phase data (Sp) and computing the clock count data (Scd) related to a frequency of the clock (Sc) from the horizontal image start coordinates (HcS) and the horizontal image termination coordinates (HcE). The display controller (4R) successively generates the phase data (Sp), then measures a value obtained by subtracting the horizontal image start coordinates (HcS) from the horizontal image termination coordinates (HcE) for each phase data (Sp) to successively store, and thereby automatically adjusts the number of waves of the clock (Sc) so that the minimum value among the values successively stored matches a pixel count (NHP) in an effective horizontal display period determined when the analog image input signal (Sia) is digitally generated. <IMAGE>
申请公布号 EP0961261(A1) 申请公布日期 1999.12.01
申请号 EP19990107443 申请日期 1999.04.27
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 SAMESHIMA, OSAMU
分类号 G09G3/20;G09G5/00 主分类号 G09G3/20
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