Method and apparatus for accessing a parallel memory buffer with serial data

摘要

A memory buffer apparatus (29) includes an extended shift register (32) and a memory (30). The extended shift register (32) shifts a plurality of serial bits to produce a multi-bit data word. The multi-bit data word has a predetermined length based on a delay interval that is a multiple of a serial bit period. The memory (30) stores the bit-slice of the multi-bit data word. The bit-slice has a length less than that of the multi-bit data word. An extended output shift register (34) can also be included in the apparatus (29). The extended output shift register (34) has a length greater than the stored bit-slice, and performs a parallel-to-serial conversion of the bit-slice output from the memory (30). <IMAGE>