发明名称 CLOCK SIGNAL DESKEWING SYSTEM
摘要 A system for distributing synchronized clock signals to spatially distributed circuits includes a pair of transmission lines, each extending between first and second sites. The transmission lines are interconnected at the second site so that an outgoing clock signal traveling on the first transmission line from the first site to the second site returns to the first site on the second transmission line. Spatially distributed deskewing circuits tap the signal transmission lines between the first and second sites. A first delay circuit in each deskewing circuit detects the outgoing clock signal on the first transmission line and produces a local clock signal that lags the outgoing clock signal by an adjustable delay time. A similar second delay circuit in each deskewing circuit delays the local clock signal by a similar adjustable delay time to produce a local reference signal. A phase lock controller in each deskewing circuit adjusts the delay times of the delay circuits so that the local reference signal is phase locked to the returning clock signal on the second transmission line. When reference signals in all deskewing circuits are phase locked to the returning clock signal, their local clock signals have similar phases regardless of the spatial distribution of the deskewing circuits that generate them.
申请公布号 EP0872069(A4) 申请公布日期 1999.12.01
申请号 EP19960943669 申请日期 1996.12.10
申请人 CREDENCE SYSTEMS CORPORATION 发明人 BEDELL, DANIEL, J.;MILLER, CHARLES, A.
分类号 H04L7/00;H04L7/033;(IPC1-7):H04L7/00 主分类号 H04L7/00
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