| 摘要 |
A test pattern generating method for a logical circuit comprises selecting failures to be detected in the logical circuit on which a test pattern is generated, selecting a target failure from all failures selected, generating a test pattern for detecting the target failure, performing a failure simulation on all selected failures by the generated test pattern, selecting the target failure from the failures not detected by the test pattern, and deleting a redundancy test pattern, which has a low failure detection rate, from the test patterns for detecting all failures. <IMAGE> |
