IEEE-BASED FLOATING-POINT UNIT

摘要

PROBLEM TO BE SOLVED: To enable variation at the time of binary floating-point calculation execution based upon the IEEE7 standards by checking a corresponding system register mask by an exception handler unit and judging that operation has been completed or restrained. SOLUTION: The floating-point unit FPU has a control input and data input register and a control and data write stage register which transfers the result of instruction execution from the floating-point unit to a storage unit through data output. A floating-point mechanism is controlled by a system register which can be set by millicode or initial program loading. When one of events is detected, the corresponding system register mask is checked to judge whether the operation has been completed or restrained. In the latter case, a floating decimal point restrains all of the update of an arbitrary mechanism which is already designed (mechanism that a user can access) and generates a similar exception code. A special condition detection unit 14 detects special conditions.