发明名称 |
Delay locked loop circuit |
摘要 |
Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.
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申请公布号 |
US5994934(A) |
申请公布日期 |
1999.11.30 |
申请号 |
US19980111875 |
申请日期 |
1998.07.08 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
YOSHIMURA, TSUTOMU;NAKASE, YASUNOBU;MOROOKA, YOSHIKAZU;WATANABE, NAOYA;KONDOH, HARUFUSA;NOTANI, HIROMI |
分类号 |
H03K5/13;G06F1/10;H03K5/00;H03L7/00;H03L7/081;H03L7/089;H03L7/095;(IPC1-7):H03L7/06 |
主分类号 |
H03K5/13 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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