发明名称 Integrated circuit and fabricating method and evaluating method of integrated circuit
摘要 A method of fabricating an integrated circuit of which a bonding condition can be evaluated simply is provided. Two external connecting electrodes are provided on the surface, via holes are formed below them, and conductive portions are formed in the via holes. Then, a first metal film is formed on a rear face of a chip and a second metal film is formed on a surface of a ceramic substrate, and then both of them are made contact and heated so as to bond the chip and the ceramic substrate. Further, when the first metal film is formed, a slit portion which no first metal film exists is provided. When the bonding condition is evaluated, a resistance between two external connecting electrodes is measured.
申请公布号 US5994716(A) 申请公布日期 1999.11.30
申请号 US19970864860 申请日期 1997.05.29
申请人 OKI ELECTRIC INDUSTRY, CO. LTD. 发明人 IKEYA, MASAHISA;INOKUCHI, KAZUYUKI
分类号 G01R31/26;H01L21/60;H01L21/66;H01L23/48;H01L23/544;(IPC1-7):H01L23/58;H01L23/04 主分类号 G01R31/26
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