发明名称 |
Scalable, high bandwidth multicard memory system utilizing a single memory controller |
摘要 |
A high speed memory interface for a processor-based computing system provides a bridge component (made up of a controller and a data path), one or more data multiplexer/buffers, and a plurality of RAS/CAS generators. The high speed memory interface allows for the expansion of the memory subsystem without additional loading on the processor/system bus and without a reduction in memory transaction performance. The interface includes a single controller for receiving memory transaction commands from the processor/system bus, and a plurality of RAS/CAS generators, for generating RAS/CAS signals in response to memory transaction commands forwarded by the controller. Each RAS/CAS generator is coupled to one or more memory banks. A data multiplexer/buffer is coupled to one or more of the memory banks, and provides an interface between the memory bank(s) and the data path.
|
申请公布号 |
US5996042(A) |
申请公布日期 |
1999.11.30 |
申请号 |
US19960766955 |
申请日期 |
1996.12.16 |
申请人 |
INTEL CORPORATION |
发明人 |
PAWLOWSKI, STEPHEN S.;MACWILLIAMS, PETER D. |
分类号 |
G06F13/16;(IPC1-7):G06F13/16 |
主分类号 |
G06F13/16 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|