| 摘要 |
A central processing unit (CPU) of a computer includes a novel prefetch cache configured in parallel with a conventional data cache. If a data cache miss occurs, the requested data is fetched from external memory and loaded into the data cache and into the prefetch cache. Thereafter, if a prefetch cache hit occurs, a prefetch address is derived, and data corresponding to the prefetch address is prefetched into the prefetch cache. This prefetching operation frequently results in the prefetch cache storing data that is requested by subsequently executed instructions in a computer program, thereby eliminating latencies associated with external memory. A software compiler of the computer ensures the validity of data stored in the prefetch cache. The software compiler alerts the prefetch cache that data stored within the prefetch cache is to be rewritten and, in response thereto, the prefetch cache invalidates the data. In this manner, data may be invalidated without requiring use of conventional cache snooping mechanisms, thereby increasing the speed with which data in cache memory may be invalidated. The ability to more quickly invalidate data in cache memory allows data previously considered "non-cachable" to be stored, and remain valid, in cache memory.
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