| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a frame synchronizing circuit, with which the price of a device can be lowered, possibility for obtaining components can be improved, the power consumption of the device can be reduced and power consumption can be decreased, while suppressing the device to handle a high-speed digital signal to a minimum without worsening adverse frame synchronization pull-in setting time and erroneous synchronizing rate. SOLUTION: Synchronous word discriminators 11-14 discriminate frame synchronism from four lines of low-speed digital signals converted by a serial/ parallel conversion circuit 2. An OR circuit 15 synthesizes the respective outputs of the synchronous word discriminators 11-14, and an aperture circuit 17 loads aperture to that synthetic output. After synchronism is established, a selector circuit 16 extracts only the output corresponding to the apparent change of a synchronous word. When narrow aperture is loaded, a frame counter circuit 22 estimates the prescribed position of the next frame. For the output of the selector circuit 16, a leading aligning/line switching circuit 23 performs leading alignment and line switching of data.</p> |
