发明名称 EVALUATION METHOD FOR SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM USING THE SAME
摘要 <p>PROBLEM TO BE SOLVED: To perform the various evaluation of debugging or the like utilizing information relating to a built-in cache memory in a semiconductor device functioning as a microprocessor. SOLUTION: In an emulation chip 10 provided with a cache memory 12 for temporarily storing the information accessed in a processor block 11 and a cache controller 13, as emulator dedicated terminals, a small number of cache hit signal terminals 16a, a cache mishit signal terminal 17a and an entry information/WAY information terminal 15a are provided. Every time of a cache hit/cache mishit, entry information/WAY information 15 is recorded, the entry information/WAY information 15 is converted to an address bus/data bus value at the time of the cache hit and displayed by utilizing the address bus/data bus value obtained through normal address bus terminal 14a and data bus terminal 18a in cache fill at the time of the cache mishit and thus, debugging is performed.</p>
申请公布号 JPH11327949(A) 申请公布日期 1999.11.30
申请号 JP19980126350 申请日期 1998.05.08
申请人 HITACHI LTD 发明人 OTAKE MASANORI;AOTO GIICHI;FUJITA HIDEYA
分类号 G06F12/08;G06F11/28;G06F15/78;(IPC1-7):G06F11/28 主分类号 G06F12/08
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