发明名称 Method for capturing ASIC I/O pin data for tester compatibility analysis
摘要 The present invention includes a modeling and testbench creation methodology which will allow a simulator to provide information regarding the state and direction of a bi-directional pad or pin. The present invention provides ATE tools all of the required data used to accurately and efficiently check for tester compatibility for which test patterns are extracted. In particular, the present invention includes a method of modeling a bi-directional I/O pad that includes the steps of providing a first signal in a first model; providing a second signal in a second model; and determining contention and direction of a resolved signal that is generated in response to at least one of the input and output signals. The first signal is a preferred output signal that is contained within an ASIC (first) model. The second signal is a preferred input signal that is contained within a testbench (second) model.
申请公布号 US5995740(A) 申请公布日期 1999.11.30
申请号 US19960773469 申请日期 1996.12.23
申请人 LSI LOGIC CORPORATION 发明人 JOHNSON, SCOTT D.
分类号 G01R31/3183;G06F17/50;(IPC1-7):G06F13/20;G06F9/455 主分类号 G01R31/3183
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