| 摘要 |
In order to verify a design of an integrated circuit in terms of a peak current density limit of electromigration specifications, a plurality of transistors, included in a given net of the integrated circuit, are assorted into a plurality of transistor groups. This assortment is based on different logical states which the given net is capable of assuming. Following this, both a lead resistance and load capacitance of the net are determined. Further, a plurality of peak currents respectively associated with the transistor groups are determined using the lead resistance and the load capacitance. Subsequently, a check is made to determine a maximum peak current among the plurality of peak currents already obtained. A peak current density of the maximum peak currents is determined using data of lead shapes, after which a check is further made to determine if the peak current density exceeds the peak current density limit of electromigration specifications.
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