High withstand voltage semiconductor device and manufacturing method thereof

摘要

An n- layer is formed on a main surface of a p-type semiconductor substrate. A p- diffusion region is formed at a surface of n- layer. A p diffusion region is formed contiguous to one end of p- diffusion region. A plurality of p diffusion regions containing p-type impurity the concentration of which is higher than that of p- diffusion region are formed in p- diffusion region. A p diffusion region is formed such that it is spaced apart from p- diffusion region. A gate electrode is formed on a surface of n- layer positioned between p diffusion region and p- diffusion region with an oxide film interposed. A drain electrode is formed in contact with a surface of p diffusion region. Furthermore, an n diffusion region is formed adjacent to p diffusion region, and a source electrode is formed in contact with both a surface of n diffusion region and a surface p diffusion region.