| 摘要 |
Is disclosed a semiconductor memory device having a self-refresh mode, the semiconductor memory device comprises a bit line precharge voltage generating circuit which is composed of a first voltage generator and a second voltage generator. The bit line precharge voltage generating circuit generates a bit line precharge voltage in response to a control signal indicating a self-refresh mode. During a time period in which the operating voltage is maintained at a first power supply voltage and the control signal is activated, the bit line precharge voltage is maintained at a voltage level between half the second power supply voltage and half the first power supply voltage though the operating voltage in the DRAM is changed from the second power supply voltage level to the first power supply voltage level. A voltage variation (or, a sense margin of a sense amplifier) on a bit line is increased, so that there is prevented a read malfunction for data '1' induced when the refresh operation is performed during the time period.
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