发明名称 |
Method and apparatus for data sample clock recovery |
摘要 |
A method and apparatus is described for recovering data sample clock rates from received isochronous streams of data packets including associated time stamp values, such as in an IEEE 1394 bus-interconnected system. The difference between consecutive time stamp values is determined by successively latching the time stamp values and applying them to a subtracter circuit to produce a difference value. This difference value is then successively decremented by a down counter, with the down counter then producing a signal pulse and loading a next difference value upon completion of the count. The pulsed signal is applied to a phase-locked loop to provide a frequency multiple, and a clock signal is correspondingly produced that has a frequency proportional to the difference between the consecutive time stamp values. Data input buffer levels may be monitored and the clock signal frequency adjusted accordingly. |
申请公布号 |
AU3792299(A) |
申请公布日期 |
1999.11.29 |
申请号 |
AU19990037922 |
申请日期 |
1999.05.11 |
申请人 |
DIGITAL HARMONY TECHNOLOGIES, L.L.C. |
发明人 |
ROBERT W. MOSES;GREGORY J. BARTLETT;ALLEN R. GOLDSTEIN;BRIAN D. KARR |
分类号 |
G06F9/445;G06F9/24;G06F9/318;G06F13/10;G06F13/38;H04J3/00;H04J3/06;H04L7/00;H04L7/033;H04L12/28;H04L12/40;H04L12/64;H04N5/21;H04N7/24 |
主分类号 |
G06F9/445 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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