发明名称 TEST METHOD AND INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To conduct a test to an integrated circuit device in a high speed without using a tester. SOLUTION: In a test method of an integrated circuit device 1 having plural pins 6 and plural flip-flops 11 which are connected to the plural pins 6 and also connected respectively in series so as to compose a scan path 3 which performs a shift motion as a shift resister at the time of the test, following steps are established, namely, a step in which a test control circuit 5, by which a test using the scan path 3 is performed, is installed beforehand in the integrated circuit device 1 in the state where the test control circuit 5 is connected to the scan path 3, and a step in which the plural pins 6 are connected respectively by an external wiring 4, and also a step in which the test using the scan path 3 is performed by the test control circuit 5, by giving a test mode signal to the test control circuit 5 in the state where the plural pins 6 are connected respectively by the external wiring 4.
申请公布号 JPH11326456(A) 申请公布日期 1999.11.26
申请号 JP19980125986 申请日期 1998.05.08
申请人 NEC CORP 发明人 MATSUZAWA HAJIME
分类号 G01R31/28;G01R31/26;G06F11/22;H01L21/66 主分类号 G01R31/28
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