发明名称 Verfahren zur Prüfsequenzerzeugung
摘要 A method for generating a test sequence for a fault in a sequential circuit to provide a high fault coverage. In one embodiment, a circuit state, which a system fails to justify, is stored as an illegal state in a step 107. In a step 103, a target fault is selected. In a step 104, the system performs its fault propagation processing to generate a test sequence and propagate the target fault from a fault location to any external output pin in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. In a step 105, the system performs its state initialization processing to generate a test sequence to transfer the state of the circuit from its initial state to a state when the fault was sensitized in such a manner that the circuit state does not coincide with the illegal state set stored in the step 107, and judges the success or failure of the sequence generation. Since the circuit state when the system fails to justify the state is stored as the illegal state so that a circuit state at the time of generating a subsequent test sequence is prevented from coinciding with the illegal state set, the possibility of the successful test sequence generation can be increased and thus the test sequence generation system can achieve a high fault coverage.
申请公布号 DE69229093(T2) 申请公布日期 1999.11.25
申请号 DE1992629093T 申请日期 1992.09.28
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. 发明人 HOSOKAWA, TOSHINORI;MOTOHARA, AKIRA;OHTA, MITSUYASU
分类号 G01R31/3183;G06F11/22;G06F11/26;G06F17/50;(IPC1-7):G06F11/22;G01R31/318 主分类号 G01R31/3183
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