| 摘要 |
A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line (<o>en</o>), including a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks comprise memory means (101-104; 201, 207; 401-408; 501, 502, 513, 514) consuming a minimum of power when they are disabled and are activated only when the value of the respective data output connection (q) has to be changed.
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