SOFTWARE CONFIGURABLE TECHNIQUE FOR PRIORITIZING INTERRUPTS IN A MICROPROCESSOR-BASED SYSTEM

摘要

A software configurable technique for prioritizing and masking interrupts in a microprocessor-based system. Contents of a first plurality of registers (100) map each of a plurality of interrupts to an appropriate one of a second plurality of registers (200) and indicate which interrupts are masked. The second plurality of registers are arranged in a predetermined priority and each contains the starting address (200) of an appropriate interrupt service routine for the corresponding interrupt. The interrupt signals are mapped to the outputs of a plurality of logical "OR" gates according to the contents of the first plurality of registers by a plurality of de-multiplexers (302) coupled to the inputs of the plurality of logical "OR" gates (312). Each logical "OR" gate corresponds to one of the second plurality of registers. A plurality of logical "AND" gates (322) are coupled to the outputs of the logical "OR" gates so as to allow only the highest priority enabled interrupt signal to enable the corresponding one of the second plurality of registers.