| 摘要 |
<p>A low power (LFSR) comprising an ordered set of register steps including memory means (1-7), wherein enabling means (F1-F7, N1-N7), enable a single current memory means (1-7) at every shift operation. Each register step comprises a low power memory means (7) consuming a minimum of power when it is disabled, feedback means (E7), an output terminal thereof being connected to an input terminal of the memory means (7), the feedback means (E7) having first and second input terminals connected to an output terminal (data7) of the memory means (7) and an output terminal (data2) of a second subsequent memory means (2), respectively, in the set. The output terminal (data1-data7) of each memory means (1-7) is connected to selection means (M1), selecting at every shift operation the output terminal (data1) of a first subsequent memory means (1) following the current memory means (7) being enabled at the current shift operation.</p> |
