Verfahren zum Testen einer integrierten Schaltungsanordnung und integrierte Schaltungsanordnung hierfür

摘要

In test mode, a pseudo-random generator (26) located inside the integrated circuit (10) generates a plurality of digital test values which are each conveyed to a digital signal processing device (22) inside the integrated circuit (10). The individual output signals of the digital processing device (22) are conveyed to a checksum arithmetic unit (30) which calculates a checksum from the plurality of processed items of data. The checksum is then used as a criterion for the integrated circuit (10) being free of defects.