Synthesizer circuit for clock signals

摘要

The synthesizer includes a multistage delay line (101 to 110). Several differential XOR gates (111 to 115) receive two outputs of each pair of delay line elements. A multiple input differential NOR gate (116) receives the output from each differential XOR gate and delivers the synthesized clock signal as an output (119). A phase locked loop logic circuit receives a reference clock signal and the output of the last delay line element and outputs a multi-bit vector. A current digital to analog (D/A) converter receives the multi-bit vector and mirrors the corresponding control current for each delay element so that the magnitude of the mirrored current controls the delay of the delay elements.