Packet distribution in a microcomputer

摘要

An integrated circuit device (11) with an address and data path (15) interconnects a CPU (12) with at least one module (14) and a memory interface (32), the module (14) having circuitry (8) to generate an event request packet and the CPU having event logic (44) to decode the packet as well as circuitry to generate addressed memory access packets, the same address and data path (15) being used for the distribution of event request packets and memory access packets. <IMAGE>