Scalable width vector processor architecture for efficient emulation

摘要

A N-byte vector processor is provided which can emulate 2N-byte processor operations by executing two N-byte operations sequentially. By using N-byte architecture to process 2N-byte wide data, chip size and costs are reduced. One embodiment allows 64-byte operations to be implemented with a 32-byte vector processor by executing a 32-byte instruction on the first 32-bytes of data and then executing a 32-byte instruction on the second 32-bytes of data. Registers and instructions for 64-byte operation are emulated using two 32-byte registers and instructions, respectively, with some instructions requiring modification to accommodate 64-byte operations between adjacent elements, operations requiring specific element locations, operations shifting elements in and out of registers, and operations specifying addresses exceeding 32 bytes.