发明名称 |
Logic circuit and method of designing the same |
摘要 |
A CMOS logic circuit consists of a domino gate serving as a logic gate 1 not disposed on a critical path and operating on a lower supply voltage (VDDL) and another domino gate serving as a logic gate 2 operating on a higher supply voltage (VDDH). An output of the logic gate 1 is an input to the logic gate 2. No level converter is arranged between the logic gates 1 and 2, and therefore, the power dissipation of the CMOS logic circuit is small. The CMOS logic circuit is designed according to a method that satisfies timing requirements and maximizes the number of logic gates that operate on the lower supply voltage (VDDL).
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申请公布号 |
US5990706(A) |
申请公布日期 |
1999.11.23 |
申请号 |
US19970827506 |
申请日期 |
1997.03.28 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
MATSUMOTO, NOBU;USAMI, KIMIYOSHI;TSUJIMOTO, JUN-ICHI |
分类号 |
H03K19/00;G06F17/50;H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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