发明名称 Methods and circuits for single-memory cell multivalue data storage
摘要 Multivalued memory cell 300 includes a latch 300 having a latching node operating between a variable voltage rail and a fixed voltage rail. Circuitry 303 allows for latching of node to a voltage level of the variable voltage rail, the voltage level at the latched node representing a data value. Circuitry 303 provides for the outputing of the voltage level from the latched node.
申请公布号 US5991191(A) 申请公布日期 1999.11.23
申请号 US19970985943 申请日期 1997.12.05
申请人 SILICON AQUARIUS, INC. 发明人 RAO, G.R. MOHAN
分类号 G11C11/419;G11C11/56;(IPC1-7):G11C11/00 主分类号 G11C11/419
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