| 摘要 |
A semiconductor device, e.g. power transistor (1, FIG. 1), has a gate or other electrode (4) connected via a test pad (15B) to a set of parallel fingers (21A-21F) in a first portion of a bond pad (12). An ESD protection device (13) is connected via a test pad (15C) to a set of parallel fingers (22A-22C) in a second portion of the bond pad (12). A voltage clamping protection device (14) is connected via a test pad (15A) to a set of parallel fingers (23A-23C) in a third portion of the bond pad (12). The three sets of fingers overlap in an interdigitated pattern defining a bond pad area (24). The transistor (1) and the protection devices (13, 14) may be independently tested and then connected to a same terminal (7C) by a wire (16) bonded over a rectangular bonded region (25) extending across the bond pad area (24). This arrangement allows for a large misalignment in the bond process while still achieving connection of the three bond pad portions. |
