发明名称 Processor
摘要 Microprocessors use a conditional branch instruction so as to change processing in accordance with conditions. According to the prior art, a NOP instruction, which causes no operation, is used when a condition is satisfied, and the use of the NOP instruction inevitably lengthens the processing time. According to the present invention, a conditional transfer instruction is included in the instruction set of a microprocessor, and a flag decoder is additionally employed. The flag decoder determines whether a condition is satisfied or not, and outputs a control signal on the basis of the determination. The control signal is supplied to the instruction decoder of the processor to make a data transfer operation effective or ineffective. Accordingly, it is not necessary to use a NOP instruction, and the processing time can be as short as possible.
申请公布号 US5991872(A) 申请公布日期 1999.11.23
申请号 US19970947750 申请日期 1997.10.09
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 SHIRAISHI, MIKIO;SAITOU, MASAKI;OKUDA, YUJI
分类号 G06F9/308;G06F9/30;G06F9/312;G06F9/32;G06F9/38;(IPC1-7):G06F13/00 主分类号 G06F9/308
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