发明名称 Delay line ramp demodulator
摘要 An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse. The pulse conversion circuitry generates a converted signal that has a level based upon the duration of the signal pulse. The sampling circuitry samples the converted signal based upon a sample pulse to generate the demodulated output based upon the level of the converted signal. The delay circuitry and pulse delay circuitry each include a plurality of cascaded semiconductive elements that, in combination, produce a desired delay duration.
申请公布号 US5990733(A) 申请公布日期 1999.11.23
申请号 US19980026062 申请日期 1998.02.19
申请人 INTERMEC IP CORP. 发明人 MAHANY, RONALD L.;SCHUSTER, THOMAS J.
分类号 H03D3/02;(IPC1-7):H03D3/02 主分类号 H03D3/02
代理机构 代理人
主权项
地址